Indian Institute of Technology Jammu, a premier technical institute in Jammu and Kashmir, has announced recruitment for Junior Research Fellow and Senior Project Associate posts, with two positions on offer. The roles are project-based research positions in VLSI Design and Test under an R&D project titled Low overhead MBIST for embedded memories in SoCs, sanctioned under the RESPOND Programme by ISRO, Department of Space, and based in the Department of Electrical Engineering.
IIT Jammu Recruitment 2026 - Junior Research Fellow and Senior Project Associate Posts
Posted 29 Sept 2026Updated 29 Sept 2026IITJMU/R&C/RP-100369/A-51
Total Vacancies
2
Last Date
05 Oct
Closed
Apply Mode
Online
Contract
Status
Application Closed
Recruitment status
Applications closed on 05 Oct 2026
- Notification14 Sept
- Applications Open
- Applications Closed05 Oct
About IIT Jammu JRF and Senior Project Associate Recruitment 2026
Job Overview
- Organization
- Indian Institute of Technology Jammu
- Advertisement No.
- IITJMU/R&C/RP-100369/A-51
- Post Name
- Junior Research Fellow (JRF) and Senior Project Associate (SPA)
- Job Location
- Jammu, Jammu and Kashmir
- Who Can Apply
- Candidates from anywhere in India (Applications are invited from the Indian nationals)
- Job Type
- Contract
- Age Limit
- Up to 40 years
- Gender
- All
- Nationality
- Indian
- Credentials Required
- Junior Research Fellow: qualified in CSIR-UGC NET including lectureship (Assistant Professorship) and GATE, or national level examinations conducted by Central Government Departments and their agencies such as DST, DBT, DAE, DOS, DRDO, MoE, ICAR, ICMR, IIT, IISc, IISER, NISER
- Tenure
- Initially for one year, may be extended depending on performance; the position is co-terminus with the project
Vacancy Breakdown
Junior Research Fellow (JRF)
1
Senior Project Associate (SPA)
1
Total2
| Post Name | Total |
|---|---|
| Junior Research Fellow (JRF) | 1 |
| Senior Project Associate (SPA) | 1 |
| Grand Total | 2 |
Eligibility Details
Requirements differ by post — open a post to see its own.
Junior Research Fellow (JRF)1 post
- Qualification
- M.E./M.Tech./MS(R) or equivalent degree in CSE/ECE/EE/Microelectronics/VLSI Design and allied subjects with 60% marks or equivalent (5% marks relaxation for SC/ST/PwD); OR B.E./B.Tech/M.Sc. in CSE/ECE/EE/Electronics/Microelectronics/VLSI Design/Embedded Systems and allied subjects with 60% marks or equivalent, and qualified in CSIR-UGC NET including lectureship (Assistant Professorship) and GATE or other national level examinations conducted by Central Government Departments and their agencies. Students awaiting results may also apply.
- Area of Specialization
- VLSI Design and Test
- Duration
- Initially for one year, may be extended depending on performance; co-terminus with the project
- Desirable
- Experience in Digital VLSI Design and Test, Memory Testing, FPGA Based Implementation, HDLs and EDA tools (Cadence, Mentor Graphics, Synopsys)
Senior Project Associate (SPA)1 post
- Qualification
- Doctoral Degree in Science/Engineering/Technology in CSE/ECE/EE/Electronics/Microelectronics/VLSI Design/Embedded Systems and allied disciplines from a recognized University or equivalent; OR M.E./M.Tech. or equivalent degree in CSE/ECE/EE/Microelectronics/VLSI Design and allied disciplines; OR B.E./B.Tech. in CSE/ECE/EE/Electronics/Microelectronics/VLSI Design/Embedded Systems and allied disciplines with 60% marks or equivalent CGPA and four years' experience in Research & Development in Industrial/Academic Institutions or Science & Technology Organizations. 5% relaxation in marks for SC/ST/PwD candidates. Students awaiting results may also apply, subject to production of the qualifying degree at the time of appointment.
- Experience
- Four years' experience in Research & Development in Industrial/Academic Institutions or Science & Technology Organizations and scientific activities and services (for B.E./B.Tech. based applicants)
- Age Limit
- Maximum 40 years
- Area of Specialization
- VLSI Design and Test
- Duration
- Initially for one year, may be extended depending on performance; co-terminus with the project
- Desirable
- Sound knowledge of Design-for-Test (DfT) Architectures, Memory Test (MBIST), MBIST Algorithms (MARCH and Non-March), SoC-level DFT integration, FPGA/ASIC prototyping, HDLs (VHDL, Verilog, System Verilog), HLLs (Python, C++) and EDA tool flows
Age Limit
Maximum 40 years for Senior Project Associate (SPA)
Age Relaxation
5 years for SC/ST, PwD/PwBD; 3 years for OBC-NCL
Selection Process
- 1Shortlisting
Candidates are shortlisted based on merit and the need for the project; possessing the prescribed qualification does not ensure an interview call.
- 2Interview
Shortlisted candidates are informed by email and interviewed on an online or offline platform.
Salary Structure
Junior Research Fellow (JRF)
Pay: Rs. 37,000/- + 20% HRA per month
Senior Project Associate (SPA)
Pay: Rs. 42,000/- + 20% HRA per month
| Post | Pay |
|---|---|
| Junior Research Fellow (JRF) | Rs. 37,000/- + 20% HRA per month |
| Senior Project Associate (SPA) | Rs. 42,000/- + 20% HRA per month |
How to Apply
- 1Open the IIT Jammu online application portal and select the contract/project staff/JRF/SRF tab
- 2Fill in the application form with correct personal, educational and contact details
- 3Upload the scanned copies of certificates, mark sheets and other supporting documents along with photograph and signature
- 4Review all details and submit the application on or before 05-10-2026
- 5Save or print a copy of the submitted application for future reference
Documents to Carry / Upload
•Updated CV
•Original and self-attested photocopies of mark sheets and certificates supporting academic qualifications
•Documents for 10th
•12th
•Graduation
•Post-graduation and experience
Important Details
- The posts are for the R&D project titled 'Low overhead MBIST for embedded memories in SoCs' sanctioned under the RESPOND Programme by ISRO, Department of Space, and are co-terminus with the project.
- Merely possessing the prescribed qualification does not ensure an interview call; candidates may be shortlisted based on merit and the need for the project.
- Shortlisted candidates must appear for the interview with an updated CV and original and self-attested photocopies of mark sheets and certificates.
- Candidates called for interview must reach IIT Jammu at their own expense
- TA/DA is not permissible for appearing in the offline interview or for joining if offered the position.
- Candidates already employed should produce a relieving certificate from their employer if selected.
Desirable Qualification
Sound knowledge in the area of Design-for-Test (DfT) Architectures, Memory Test (MBIST), MBIST Algorithms (MARCH and Non-March), SoC-level DFT integration, FPGA/ASIC prototyping. Programming skills in HDLs (VHDL, Verilog, System Verilog) and HLLs (Python, C++), and EDA design automation tool flow in EDA tools (Cadence, Synopsys, etc.).
Address for Correspondence
Dr. Satyadev Ahlawat, Indian Institute of Technology Jammu, Department of Electrical Engineering, P.O. Nagrota, Jagti, Jammu, 182211, India. Email: [email protected]
Contact
Email: [email protected]
Frequently Asked Questions
Can students awaiting their final results apply for these posts?
Yes. The notification allows students awaiting results to apply, provided they produce the qualifying degree at the time of appointment.
Is TA/DA paid for attending the interview or for joining?
No. Candidates called for the interview must reach IIT Jammu at their own expense, and TA/DA is not permissible for appearing in the offline interview or for joining if the position is offered.
Who can apply for these positions?
Applications are invited from Indian nationals interested in the Junior Research Fellow and Senior Project Associate posts on the ISRO-funded R&D project.
Spotted a mistake in this post? Report it
Tags
Organization
Location
Qualifications