Maulana Abul Kalam Azad University of Technology (MAKAUT), a state university in Nadia, West Bengal, has invited applications for the post of Project Associate-I. A total of two positions are on offer under a MeitY-sponsored project in the Department of Microelectronics and VLSI Technology. The role is contractual and project-based, involving work on an analog digital mix signal processor architecture for signal processing research.
MAKAUT Recruitment 2026 - Project Associate-I Posts
Posted 02 Oct 2026Updated 02 Oct 2026MAKAUT/RE/ADVT./Project Associate-I/104/454
Total Vacancies
2
Last Date
11 Oct
Closed
Apply Mode
Email
Contract
Status
Application Closed
Recruitment status
Applications closed on 11 Oct 2026
- Notification25 Sept
- Applications Open
- Applications Closed11 Oct
About MAKAUT Project Associate-I Recruitment 2026
Job Overview
- Organization
- Maulana Abul Kalam Azad University of Technology
- Advertisement No.
- MAKAUT/RE/ADVT./Project Associate-I/104/454
- Post Name
- Project Associate-I
- Job Location
- West Bengal
- Who Can Apply
- Candidates from anywhere in India (Applications are invited from Indian citizens)
- Job Type
- Contract
- Age Limit
- Up to 35 years
- Gender
- All
- Nationality
- Indian
- Tenure
- Initially for one year or till the end of the financial year, annually extendable till the end of the project (up to February 2027), subject to satisfactory performance
Vacancy Breakdown
Project Associate-I
2
| Post Name | Total |
|---|---|
| Project Associate-I | 2 |
Eligibility Details
Project Associate-I
BE/B.Tech in Electronics & Communication Engineering/Microelectronics & VLSI Technology/Embedded System/VLSI Design/EE/AEIE/CSE/EEE/IT with 60% marks or CGPA of 6.75 and above. CSIR-UGC NET/GATE preferred for higher fellowship.
| Post | Qualification |
|---|---|
| Project Associate-I | BE/B.Tech in Electronics & Communication Engineering/Microelectronics & VLSI Technology/Embedded System/VLSI Design/EE/AEIE/CSE/EEE/IT with 60% marks or CGPA of 6.75 and above. CSIR-UGC NET/GATE preferred for higher fellowship. |
Age Limit
Maximum 35 years
Selection Process
- 1Shortlisting
Applications are screened against the eligibility criteria and only shortlisted candidates are intimated by email.
- 2Interview
Shortlisted candidates are called for an interview at a later date, which is intimated by email.
Salary Structure
Rs. 31,000 + HRA (for candidates selected through CSIR-UGC NET/GATE or a National level examination of the Central Government) or Rs. 25,000 + HRA (for others), as per University norms
How to Apply
- 1Prepare a CV with details of qualifications, age, email, mobile number and experience
- 2Fill the application form enclosed with the notification and scan it to PDF
- 3Attach self-attested copies of educational certificates, experience certificates, ID proof and a recent passport-size photograph
- 4Mention the post applied for in the subject line of the email
- 5Email the CV, scanned application form and documents to [email protected] on or before 11 October 2026
- 6Fill the Google form linked in the notification
- 7Keep a copy of the sent email for future reference
Documents to Carry / Upload
•CV
•Filled application form in PDF (scan)
•Self-attested copies of educational certificates
•Experience certificates
•ID proof
•Recent passport-size photograph
•Original testimonials for verification at interview or joining
Important Details
- The assignment is purely temporary and coterminous with the MeitY-sponsored project, which runs up to February 2027.
- All original testimonials must be produced for verification at the interview or joining.
- No TA/DA is paid for attending the interview or joining.
- All terms and conditions follow MeitY guidelines.
- Only shortlisted candidates are intimated by email, so applicants should check their email regularly.
Project Details
Project Title
Details: Analog Digital Mix Signal Processor - A novel architecture for signal processing
Funding
Details: Ministry of Electronics & Information Technology (MeitY), Government of India, under C2S
Department
Details: Microelectronics and VLSI Technology, MAKAUT, WB, Haringhata, Nadia, West Bengal - 741249
Principal Investigator
Details: Dr. Mihir Kumar Mahata, Associate Professor (on Contract), Microelectronics and VLSI Technology, MAKAUT, WB
Tenure of Sponsored Project
Details: Up to February 2027
| Item | Details |
|---|---|
| Project Title | Analog Digital Mix Signal Processor - A novel architecture for signal processing |
| Funding | Ministry of Electronics & Information Technology (MeitY), Government of India, under C2S |
| Department | Microelectronics and VLSI Technology, MAKAUT, WB, Haringhata, Nadia, West Bengal - 741249 |
| Principal Investigator | Dr. Mihir Kumar Mahata, Associate Professor (on Contract), Microelectronics and VLSI Technology, MAKAUT, WB |
| Tenure of Sponsored Project | Up to February 2027 |
Fellowship and HRA
- Rs. 31,000 + HRA as per University norms for scholars selected through National Eligibility Tests (CSIR-UGC NET including lectureship) or GATE, or through a selection process of National level examinations conducted by the Central Government and its agencies and institutions
- Rs. 25,000 + HRA as per University norms for others who do not fall under the above
Desirable Qualifications
- Knowledge of EDA tools, Chip Design, LINUX, etc.
- Knowledge of VLSI design
Contact
Email: [email protected]
Spotted a mistake in this post? Report it